This is a very typical situation in which we have a 3.3V system (e.g. most of 32-bit systems, such as uChip<\/a>), and we need to send data to an older 5V system.<\/p>\n\n\n\n First of\nall, we need to consider which kind of 5V system we are interfacing. In\nparticular, we need to know:<\/p>\n\n\n\n For CMOS\ninputs, the input current is typically around 1uA or less, therefore there is\nno such a concern. For TTL devices, the input current might be even more than 1\nmA (see for instance 7400 datasheet). Therefore, when interfacing with TTL\ninputs, some additional care should be taken, as we will explain on a\ncase-by-case basis.<\/p>\n\n\n\n Another,\nand much more important, aspect is represented by the logic levels. <\/p>\n\n\n\n In fact, 5V TTL and 5V CMOS inputs have different logic levels, therefore some of the solutions we will present will be adequate for some inputs, but these could not work reliably for other inputs types.<\/p>\n\n\n\n The main ways to interface a 3.3V output to a 5V input are:<\/p>\n\n\n\n This is the simplest way. This solution \u201calmost always\u201d works, but with some important warnings.<\/p>\n\n\n\n First, when interfacing with TTL inputs, any \u201cmodern\u201d CMOS output will work, as the high level output voltage of a 3.3V CMOS is close to 3.3V (note! The actual output voltage depends on the output current. For heavily loaded outputs, the output levels might vary of 0.5V or more!), still the minimum high-level input voltage for a TTL is 2V. Similarly, if not too much heavily loaded, the low-level output voltage of a CMOS is lower than the maximum low-level TTL input voltages. <\/p>\n\n\n\n We wrote \u201cmodern\u201d CMOS because older CMOS chips (e.g. CD4xxx series) have a very high output impedance, therefore they cannot sink\/source too much current (you generally do not want to sink\/source more than 0.5 mA). Trying to get too much current will make the output voltage shift too much. Older TTL chips have an input current, which might exceed 1mA. Almost all modern CMOS devices (e.g. the GPIOs of MCUs) allows driving a much higher current without problems.<\/p>\n\n\n\n Second, when interfacing to a 5V CMOS devices, this might<\/em> work, but not reliably. In fact, the high level input voltage of a 5V CMOS is 3.5V. This is even higher<\/em><\/strong> than the maximum output voltage you might expect from a 3.3V system (i.e. 3.3V). Furthermore care should be taken when driving a digital non hysteretic\ninput close to the logic level threshold, as current consumption would occur.\nIn fact, consider the simple CMOS inverter, shown below: when the input voltage\nis close to the VDD\/2, both MOSFETs are in the ON state, therefore a direct\npath current will flow from VDD to GND.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n The 74HCTxx family series are CMOS devices with TTL compatible logic levels (all the other 5V logic families that have TTL compatible input levels will work too) . In particular, the input high-voltage level is 2V, which is well below the CMOS high output voltage. By inserting any logic gate (see examples below) with TTL-compatible input levels between your systems, you create a suitable voltage level translator.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n With the\ndirect connection to a 5V CMOS input, we saw that the main issue was the high\nlevel output voltage of the 3.3V output, which is not high enough to be just in\nthe safe region (3.3V at most, vs 3.5V minimum). Instead, the maximum voltage\nof a low level CMOS input is 30% of VDD, i.e 1.5V in a 5V system. Therefore, if\nwe could add small offset to the CMOS output, that would be great. For this\nreason, one could simply ad a diode and a pull-up resistor. <\/p>\n\n\n\n However, in\nthis way, current will flow into the output protection diodes of our 3.3V\nsystem. Such current should be made as small as possible, to avoid damaging the\n3.3V system. <\/p>\n\n\n\n A better\nsolution is to use an additional diode. Since the new diode is directly connected\nto the 3.3V rail (it does not have to pass through our IC), the current will\nflow preferably there.<\/p>\n\n\n\n Still, both\nthese solutions has an intrinsic problem: if the 3.3V system is really low\npower, then of course it will consume a very low current. If the total current\nconsumption is lower than the current flowing into the resistor, then\neffectively, the 3.3V rail will be powered by the 5V, through the resistor and\ndiode. <\/p>\n\n\n\n This might\nbe an issue, as, if no enough current is drawn by the 3.3V system, the 3.3V\nvoltage might increase up to about 4.3V, which could damage the 3.3V system\nitself.<\/p>\n\n\n\n A simple solution is to put a second resistor, which draws at least the current that would flow into D2 (about 1V\/R1. Therefore R2 should be 3.3 times R1 or less). <\/p>\n\n\n\n The value\nof the pull-up resistor should be calculated so that:<\/p>\n\n\n\n Advantages:\n<\/p>\n\n\n\n Disadvantages: <\/p>\n\n\n\n We can\nintroduce an offset also using a resistor divider too.<\/p>\n\n\n\n This simple\nsolution is cheaper (but somewhat slower) than the diode-offset, and still has\nthe problem of current flowing into the output pin. <\/p>\n\n\n\n A better solution is to add a dummy load to the output, that will adsorb the current coming from the 5V through R1 and R2. Another way to view this, is that, disconnecting the output, with the calculated value, R1-R2-R3 will form a resistor divider and the voltage across R3 would be 3.3V at most. The values indicated in the figures are expressed in terms or a generic \u201cR\u201d value.<\/p>\n\n\n\n When the output is 0, the voltage will be 5V * (R2\/(R1+R2)), i.e. 1V, which is below the 1.5V threshold. When the output is 3.3V, the voltage will be 5V * (R2\/(R1+R2)) + 3.3V * (R1\/(R1+R2)) = 3.64V. Better high-level values can be achieved by adjusting the R1\/R2 ratio, but you must take into account that the voltage should be smaller than 1.5V, when the output is at 0V.<\/p>\n\n\n\n Note: we took 0 and 3.3V as the CMOS output voltages, when the output is low and high, respectively. While, this time, there is no problem (unless R3 is too low) about the high level voltage (as it is pulled up by R1+R2), the low-level voltage will increase according to the current flowing into the output.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n As we did\nin the other article, a simple MOSFET\/BJT can be used, if an inverted signal\ncan be accepted or is desired. Otherwise, an additional stage can be used.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n In the\n5-to-3.3V article, we showed this little circuit, and we told that it is\nbidirectional. Indeed, it can be used for 3-to-5V translation too!<\/p>\n\n\n\n The working\nprinciple is simple. When the output is at 3.3V, the MOSFET will be in the\nOFF-state, as VGS=0V, therefore the output is held at 5V by the pull-up resistor.\nIf the output is low, then VGS is 3.3V. Assuming a MOSFET with a logic-level\nthreshold (it should be fully-on when VGS = 2.5V), the MOSFET will turn on,\npassing the low-level value to the 5V input.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages: <\/p>\n\n\n\n This is the\nbrother of the previous solution, except it uses a BJT. The working principle\nis the same (as we also explained in the previous article). It shares the same\nbenefits of the previous circuit, but it also introduces some additional\ndrawbacks.<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages: <\/p>\n\n\n\n A dedicated level translator IC, such as 74LVC1T245, will do everything you need, with better performances with respect to discrete solutions, but at a much higher price. <\/p>\n\n\n\n There are many variants, such as with more channels (74LVC8T245, 74LVC16T245), or different logic family (74ALVT162245), with different speeds (and prices).<\/p>\n\n\n\n Use this solution when you require a high performance 3.3V to 5V level translation (typically in high speed buses, clocks, etc.)<\/p>\n\n\n\n Advantages:<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n As shown in\nthe previous article, this solution is \u201cany voltage-to any voltage\u201d translator,\ntherefore it can be used also for the 3.3V to 5V translation. There are 4\nconfigurations, depending on your requirements.<\/p>\n\n\n\n Beware that\nsome configurations require a strong low-level output driver (while nothing is\nrequested in terms of high-level output strength), while the other requires a\nstrong high-level output driver. <\/p>\n\n\n\n Similarly,\nthe output will provide a strong pull-up\/down path (through the coupler), and a\nweaker one (through the pulldown\/up resistor, respectively).<\/p>\n\n\n\n Instead of\nusing standards optoisolators, you can use more recent devices, based on capacitive,\ngiant magnetoresistive or magnetic couplings, even though these are much more\nexpensive, typically.<\/p>\n\n\n\n Advantages:\n<\/p>\n\n\n\n Disadvantages:<\/p>\n\n\n\n We have shown some of the main methods of interfacing a 3.3V to a 5V system! We will keep updating this post if we find some other interesting techniques! For the opposite direction, i.e. 5V to 3.3V interfacing, refer to this article<\/a>!<\/p>\n","protected":false},"excerpt":{"rendered":" Introduction In a previous article we dealt with the problem of interfacing a 5V output signal to a 3.3V system. In this article we cover the opposite problem: we have a 3.3V output and we need to drive a 5V… (READ MORE)<\/a><\/p>\n","protected":false},"author":2,"featured_media":660,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"categories":[28],"tags":[],"class_list":["post-655","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-logic-level-conversion"],"_links":{"self":[{"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/posts\/655"}],"collection":[{"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/comments?post=655"}],"version-history":[{"count":20,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/posts\/655\/revisions"}],"predecessor-version":[{"id":1242,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/posts\/655\/revisions\/1242"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/media\/660"}],"wp:attachment":[{"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/media?parent=655"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/categories?post=655"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/next-hack.com\/index.php\/wp-json\/wp\/v2\/tags?post=655"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/Levels.png\")
\n\n\n\nDIRECT\nCONNECTION<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/directConnection.png\")
\n\n\n\n
Still, why this generally works ? The answer is due to the actual threshold logic level, which is 2.5V for a 5V CMOS. Any voltage above 2.5V would be read as 1, and any voltage below 2.5V would be read as 0.
However, the actual threshold level might shift with temperature and aging: operating between the two logic levels region is not safe. Any noise or disturbance might produce a glitch at the output. If your system must work reliably, then you need other solutions, as shown below.<\/p>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/inverter.png\")
\n\n\n\nUSING A 74HCTxx GATE (or any other logic family with TTL compatible inputs) <\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/04\/Gate.png\")
\n\n\n\nUSING A DIODE OFFSET<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/singleDiodeOffset.png\")
\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/diodeOffset.png\")
\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/offsetBleed.png\")
\n\n\n\nRESISTOR OFFSET <\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/ResistorOffset-1.png\")
\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/ResistorOffsetBleeder.png\")
\n\n\n\nBJT\/MOSFET INVERTER<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/bjtInverter.png\")
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/MOSETInverter.png\")
\n\n\n\nSERIES MOSFET<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/MOSFETTranslator.png\"){kind=spacer}
\n\n\n\nSERIES BJT<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/BJTTranslator.png\"){kind=spacer}
\n\n\n\nLEVEL TRANSLATOR IC<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/02\/translator.png\"){kind=spacer}
\n\n\n\nOPCOUPLER\/ISOLATOR<\/h3>\n\n\n\n
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/11\/Optocoupler_NINV.png\")
\n\n\n\n![\"\"](\"https:\/\/next-hack.com\/wp-content\/uploads\/2020\/11\/Optocoupler_INV.png\")
\n\n\n\nConclusions<\/h2>\n\n\n\n